This position is for a DFT Design Engineer inside the Atom CPU DFX Design For Test and Debug team which is part of the Atom CPU RTL Development organization.
As a DFT Design Engineer in the Atom CPU team, you will work directly with the CPU design and implementation teams to implement world class design for test and debug solutions.
The successful candidate will perform one or more of the following tasks in this role:
- Write RTL for DFT blocks and functional safety blocks and work with verification teams to validate these blocks
- Apply the ATPG flow in both block level and full-chip level and ensure we can hit the scan test coverage goals
- Provide support to post silicon teams and help to debug the silicon issues
- MS or PhD in Electrical or Computer engineering with a DFT focus or the equivalent industry experience
- Must have a strong background in DFT. Minimum 2+ years of work experience with DFT with Master's degree; 0+years of work experience with a strong DFT background with PhD degree.
- A good understanding of general CPU architecture and strong RTL coding skills
- Hands-on experience on the ATPG tools, which includes ATPG flow set up, scan DRC debug and low fault coverage analysis
- A strong gate level simulation and debug capability for ATPG patterns-
- Familiarity with Functional Safety standards
The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.
Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.
Click here for more info: http://jobs.intel.com/ShowJob/Id/1465908/DFT-Design-Engineer/
• Post ID: 27981677 austin